Freescale Semiconductor /MKM14ZA5 /AFE /CKR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as CKR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (00)CLS0 (0000)DIV

DIV=0000, CLS=00

Description

Clock Configuration Register

Fields

CLS

Clock Source Select

0 (00): mod_clk0

1 (01): mod_clk1

2 (10): mod_clk2

3 (11): mod_clk3

DIV

Clock Divider Select

0 (0000): divide by 1

1 (0001): divide by 2 (default)

2 (0010): divide by 4

3 (0011): divide by 8

4 (0100): divide by 16

5 (0101): divide by 32

6 (0110): divide by 64

7 (0111): divide by 128

8 (1xxx): divide by 256

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